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Espressif Systems /ESP32-C3 /APB_SARADC /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (APB_SARADC_THRES1_LOW_INT_ST)APB_SARADC_THRES1_LOW_INT_ST 0 (APB_SARADC_THRES0_LOW_INT_ST)APB_SARADC_THRES0_LOW_INT_ST 0 (APB_SARADC_THRES1_HIGH_INT_ST)APB_SARADC_THRES1_HIGH_INT_ST 0 (APB_SARADC_THRES0_HIGH_INT_ST)APB_SARADC_THRES0_HIGH_INT_ST 0 (APB_SARADC2_DONE_INT_ST)APB_SARADC2_DONE_INT_ST 0 (APB_SARADC1_DONE_INT_ST)APB_SARADC1_DONE_INT_ST

Description

digital saradc int register

Fields

APB_SARADC_THRES1_LOW_INT_ST

saradc thres1 low interrupt state
APB_SARADC_THRES0_LOW_INT_ST

saradc thres0 low interrupt state
APB_SARADC_THRES1_HIGH_INT_ST

saradc thres1 high interrupt state
APB_SARADC_THRES0_HIGH_INT_ST

saradc thres0 high interrupt state
APB_SARADC2_DONE_INT_ST

saradc2 done interrupt state
APB_SARADC1_DONE_INT_ST

saradc1 done interrupt state

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data